3 / 11 page  Silego Technology Inc. (408) 327-8800 SLGSSTVF16859H/V 3 PRELIMINARY Data is subject to change. May 28, 2003 General Description The 14-bit SLGSSTVF16859 is a registered buffer designed for 2.3V to 2.7V VDD operating range. Inputs are SSTL_2 levels, except for the LVCMOS RESET input. Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signal (RESET). The rising edge of CLK (crossing with CLK falling) is used to register the Data. RESET, an LVCMOS asynchronous signal, is intended for use at the time of power-up. RESET must be held at a logic “Low” level during power up. This ensures defined outputs before a stable CLK/CLK is supplied. The SLGSSTVF16859 supports low-power standby operation. Setting RESET pin to a logic “low” disables (CLK/ CLK) receivers, and allows floating inputs to all other receivers as well (D, VREF , CLK/CLK). Additionally, all inter- nal registers are reset, and outputs (Q) are set “low”. RESET input pin must always be driven to a valid logic state “high” or “low”. SLGSSTVF16859H Pin Description: PIN NUMBER PIN NAME TYPE DESCRIPTION 1,17,2,19,3,20,4, 21,5,22,8,23,9,24, 10,25,11,28,12, 29,13,30,14,31, 16,32 QA/B (13:1) OUTPUT Q-Outputs 7,15,26,34,39, 43,50,58,63 GND POWER Ground 6,18,27,33,38, 47,59,64 VDDQ POWER Output supply voltage 62,61,57,56,55, 53,52,44,42,41, 40,36,35 D (13:1) INPUT D-Inputs 48 CLK INPUT Positive clock input 49 CLK INPUT Negative clock input 37, 46 VDD POWER Core supply voltage 51 RESET INPUT Reset (active low) 45 VREF INPUT Input reference voltage |
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