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ACE25QC200GLFMLTH Datasheet(PDF) 27 Page - ACE Technology Co., LTD.

Part # ACE25QC200GLFMLTH
Description  2M BIT SPI NOR FLASH
PDF  64 Pages
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Manufacturer  ACE [ACE Technology Co., LTD.]
Direct Link  http://www.ace-ele.com
Logo ACE - ACE Technology Co., LTD.

ACE25QC200GLFMLTH Datasheet(HTML) 27 Page - ACE Technology Co., LTD.

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ACE25QC200GL
2M BIT SPI NOR FLASH
VER 1.1
27
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through two pins SI, SO, /WP and /HOLD and four Dummy
clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad
Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can operate at the highest possible frequency of fC (see AC Electrical
Characteristics). The Fast Read Quad I/O instruction can further reduce instruction overhead through
setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14.
The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is
raised and then lowered) does not require the EBh instruction code, as shown in Figure 15. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFh on SI for the next instruction (8 clocks), to ensure M4 = 1 and return the
device to normal operation.
Figure13. Fast Read Sequence Diagram (Previous command set (M5-4) =(1,0))



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