SH7706 datasheet(21/709 Pages) RENESAS

21 / 709 page

Rev. 4.00, 03/04, page xxi of xlvi

Contents

Section 1 Overview...........................................................................................

1.1

Feature...............................................................................................................................

1.2

Block Diagram ..................................................................................................................

1.3

Pin Assignment .................................................................................................................

1.4

Pin Function ......................................................................................................................

Section 2 CPU................................................................................................... 13

2.1

Register Description..........................................................................................................13

2.1.1

Privileged Mode and Banks .................................................................................

2.1.2

General Registers .................................................................................................

2.1.3

System Registers ..................................................................................................

2.1.4

Control Registers .................................................................................................

2.2

Data Formats .....................................................................................................................

2.2.1

Data Format in Registers......................................................................................

2.2.2

Data Format in Memory.......................................................................................

2.3

Instruction Features...........................................................................................................

2.3.1

Execution Environment........................................................................................

2.3.2

Addressing Modes ...............................................................................................

2.3.3

Instruction Formats ..............................................................................................

2.4

Instruction Set ...................................................................................................................

2.4.1

Instruction Set Classified by Function .................................................................

2.4.2

Instruction Code Map ..........................................................................................

2.5

Processor States and Processor Modes..............................................................................

2.5.1

Processor States ...................................................................................................

2.5.2

Processor Modes ..................................................................................................

Section 3 Memory Management Unit (MMU) ................................................. 51

3.1

Role of MMU....................................................................................................................51

3.1.1

This LSI's MMU ..................................................................................................

3.2

Register Description..........................................................................................................56

3.2.1

Page Table Entry Register High (PTEH) .............................................................

3.2.2

Page Table Entry Register Low (PTEL) ..............................................................

3.2.3

The Translation Table Base Register (TTB) ........................................................

3.2.4

The TLB Exception Address Register (TEA) ......................................................

3.2.5

MMU Control Register (MMUCR) .....................................................................

3.3

TLB Functions ..................................................................................................................

3.3.1

Configuration of the TLB ....................................................................................

3.3.2

TLB Indexing.......................................................................................................

3.3.3

TLB Address Comparison ...................................................................................

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