SH7751 datasheet(39/1105 Pages) RENESAS

39 / 1105 page

Rev. 3.0, 04/02, page xxxvii of xxxviii

Table 23.28

Peripheral Module Signal Timing (1) .............................................................. 1015

Table 23.29

Peripheral Module Signal Timing (2) .............................................................. 1017

Table 23.30

PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1)...................... 1023

Table 23.31

PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2)...................... 1024

Table 23.32

PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings

in Non-Host Mode) (1) ................................................................................... 1026

Table 23.33

PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings

in Non-Host Mode) (2) ................................................................................... 1026

Table 23.34

PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings

in Non-Host Mode) ........................................................................................ 1027

Table A.1

Address List ................................................................................................... 1031

Table C.1

Clock Operating Modes (SH7751) .................................................................. 1041

Table C.2

Clock Operating Modes (SH7751R)................................................................ 1041

Table C.3

Area 0 Memory Map and Bus Width............................................................... 1042

Table C.4

Endian............................................................................................................ 1042

Table C.5

Master/Slave .................................................................................................. 1042

Table C.6

Clock Input .................................................................................................... 1042

Table C.7

PCI Mode....................................................................................................... 1043

Table D.1

Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable,

Disable Common)........................................................................................... 1044

Table D.2

Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable) . 1046

Table D.3

Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable) 1047

Table D.4

Handling of Pins When PCI is Not Used ......................................................... 1049

Table H.1

SH7751 Series Models.................................................................................... 1063

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