SH7729R datasheet(21/855 Pages) RENESAS

21 / 855 page

Rev. 5.0, 09/03, page xxi of xlvi

4.6

Cautions............................................................................................................................. 140

Section 5 Cache .................................................................................................................... 143

5.1

Overview ........................................................................................................................... 143

5.1.1

Features ................................................................................................................ 143

5.1.2

Cache Structure .................................................................................................... 143

5.1.3

5.2

Register Descriptions......................................................................................................... 145

5.2.1

Cache Control Register (CCR) ............................................................................. 145

5.2.2

Cache Control Register 2 (CCR2) ........................................................................ 146

5.3

Cache Operation ................................................................................................................ 148

5.3.1

Searching the Cache ............................................................................................. 148

5.3.2

Read Access ......................................................................................................... 150

5.3.3

Write Access ........................................................................................................ 150

5.3.4

Write-Back Buffer ................................................................................................ 150

5.3.5

Coherency of Cache and External Memory.......................................................... 151

5.4

Memory-Mapped Cache .................................................................................................... 151

5.4.1

Address Array ...................................................................................................... 151

5.4.2

Data Array ............................................................................................................ 152

5.5

Usage Examples ................................................................................................................ 154

5.5.1

Invalidating a Specific Entry ................................................................................ 154

5.5.2

Invalidating a Specific Address............................................................................ 155

5.5.3

Reading the Data of a Specific Entry ................................................................... 155

Section 6 X/Y Memory ...................................................................................................... 157

6.1

Overview ........................................................................................................................... 157

6.1.1

Features ................................................................................................................ 157

6.2

X/Y Memory Access from CPU........................................................................................ 158

6.3

X/Y Memory Access from DSP ........................................................................................ 160

6.4

X/Y Memory Access from DMAC ................................................................................... 160

Section 7 Interrupt Controller (INTC) ........................................................................... 161

7.1

Overview ........................................................................................................................... 161

7.1.1

Features ................................................................................................................ 161

7.1.2

Block Diagram ..................................................................................................... 162

7.1.3

Pin Configuration ................................................................................................. 163

7.1.4

7.2

Interrupt Sources ............................................................................................................... 165

7.2.1

NMI Interrupt ....................................................................................................... 165

7.2.2

IRQ Interrupts ...................................................................................................... 165

7.2.3

IRL Interrupts ....................................................................................................... 166

7.2.4

PINT Interrupts .................................................................................................... 168

7.2.5

On-Chip Peripheral Module Interrupts................................................................. 168

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