STW4810 datasheet(62/72 Pages) STMICROELECTRONICS

62 / 72 page

5 Electrical and timing characteristics

STw4810

62/72

Rev3

5.6

SD/MMC card interface

Table 50.

SD/MMC card interface

Symbol

Description

Test conditions

Min.

Typ.

Max.

Units

VMMC regulator specifications (PDN_VMMC = 1)

VBAT

Input voltage

VOUT = 3 V

VOUT = 2.85 V

VOUT = 1.8 V

3.25

3.1

2.7

3.6

4.8

VOUT

Output voltage

-3%

2.85

1.8

+3%

IOUT

Output current

150

ISHORT

Short circuit current

limitation

240

360

600

Quiescent current

IOUT = 0 mA

µA

ILKG

Power-down

current

PDN_VMMC = 0

µA

PSRR(1)

Power supply

rejection

IOUT = 150 mA

Vpp = 0.3 V

f < 20 kHz

LIR

(1)

Line regulation

VOUT=2.85 V

VBAT: [3.1; 4.8]V

5mV

LDR

(1)

Load regulation

VOUT=2.85 V

IOUT= [1; 150] mA

LIRT

Transient line

regulation

VOUT=2.85 V

VBAT: 3.1 to 3.4V

tR = tF = 10 µs.

2mV

LDRT

Transient load

regulation

IOUT = [1; 150] mA

tR = tF = 1 µs

Settling time

OFF->ON

IOUT = 0 mA

100

µs

Discharge time

ON>OFF

IOUT = 0 mA

1ms

Bus line specifications

RA(2)

Pull-up resistor

To prevent bus

floating

1.5

Ω

Pull-down resistor

To prevent bus

floating

1.5

Ω

fDT

Clock frequency

data transfert mode

With CL = 30pF

MHz

fID

Clock frequency

identification mode

With CL = 30pF

400

KHz

STW4810 Datasheet(PDF) 62 Page - STMicroelectronics

STW4810 Datasheet(HTML) 62 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL