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PL680-37 Datasheet(PDF) 4 Page - PhaseLink Corporation

Part # PL680-37
Description  38-640MHz Low Phase Noise XO
PDF  10 Pages
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Manufacturer  PLL [PhaseLink Corporation]
Direct Link  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PL680-37 Datasheet(HTML) 4 Page - PhaseLink Corporation

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(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
4.6
V
Input Voltage, dc
VI
-0.5
VDD+0.5
V
Output Voltage, dc
VO
-0.5
VDD+0.5
V
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature*
TA
-40
85
°C
Junction Temperature
TJ
125
°C
Lead Temperature (soldering, 10s)
260
°C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
FXIN
Parallel Fundamental Mode
19
40
MHz
Crystal Loading Rating
CL (xtal)
17.7
pF
Crystal Shunt Capacitance
C0 (xtal)
5
pF
Recommended ESR
RE
AT cut
30
Note: Crystal Loading rating: 17.7pF is the loading the crystal sees from the XO chip. It is assumed that the crystal will be at nominal frequency at this
load. If the crystal requires less load to be at nominal frequency, then a capacitor can placed in series with the crystal. If the crystal requires more
load to be at nominal frequency, capacitors can be placed from XIN and XOUT to ground. This however may reduce the oscillator gain.
3. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
PECL/LVDS/CMOS
38MHz<Fout<320MHz
65/45/30
Supply Current,
Dynamic (with
Loaded Outputs)
IDD
PECL/LVDS
320MHz<Fout<640MHz
90/70
mA
Operating Voltage
VDD
2.25
3.63
V
Output Clock
Duty Cycle
@ 50% VDD (CMOS)
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
45
45
45
50
50
50
55
55
55
%
Short Circuit
Current
±50
mA
Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.



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