Preliminary

PLL103-03

DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 08/28/00 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

FBOUT

1

O

Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.

BUF_IN

13

I

Reference input from chipset. 3.3V input for STANDARD SDRAM mode;

2.5V input for DDR-ONLY mode.

PD

36

I

Power Down Control input. When low, it will tri-state all outputs.

SEL_DDR

48

I

Input configure for DDR-ONLY mode or STANDARD SDR mode.

1 = DDR-ONLY mode (when VDD3.3_2.5 select 2.5V);

0 = SDR mode (when VDD3.3_2.5 select 3.3V).

In DDR-ONLY mode, all outputs will be configured as DDR outputs.

In STANDARD SDR mode, pin 4, 5, 6, 7, 10, 11, 15, 16, 19, 20, 21

and 22 will be configured as STANDARD SDR outputs, and pin 27,

28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as

DDR outputs.

DDR[6:11]T

28,30,34,

39,43,45

O

These outputs provide True copies of BUF_IN.

DDR[6:11]C

27,29,33,

38,42,44

O

These outputs provide complementary copies of BUF_IN.

DDR[0,1:5]T_SDRA

M [10,0,2,4,6,8]

4,6,10,15,19

, 21

O

When SEL_DDR=1, these outputs provide DDR mode outputs; when

SEL_DDR=0, these outputs provide standard SDRAM mode outputs.

Voltage swing depends on VDD3.3_2.5.

DDR[0,1:5]C_SDRA

M [11,1,3,5,7,9]

5,7,11,16,20

, 22

O

When SEL_DDR=1, these outputs provide complementary copies of

BUF_IN; when SEL_DDR=0, these outputs provide standard SDRAM

mode outputs. Voltage swing depends on VDD3.3_2.5.

VDD3.3_2.5

2,8,12,17,23

P

When VDD=2.5V, SEL_DDR=1. DDR-ONLY mode is selected; when

VDD=3.3V, SEL_DDR=0. STANDARD SDRAM mode is selected.

VDD2.5

32,37,41,47

P

2.5V power supply.

GND

3,9,14,18,26

,

31,35,40,46

P

Ground.