PLL650-03

Low EMI Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Full CMOS output swing with 40-mA output drive

capability. 25-mA output drive at TTL level.

• Advanced, low power, sub-micron CMOS processes.

• 25MHz fundamental crystal or clock input.

• 4 outputs fixed at 50MHz with output disable, 1 output

selectable at 25MHz or 100MHz with output disable

• SDRAM selectable frequencies of 66.6, 75, 83.3, 100MHz

(Double Drive Strength).

• Spread spectrum technology selectable for EMI

reduction from

±0.5%, ±0.75% center for SDRAM and

CPU.

• Zero PPM synthesis error in all clocks.

• Ideal for Network switches.

• 3.3V operation.

•

DESCRIPTION

The PLL 650-03 is a low cost, low jitter, and high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques, the chip

accepts 25.0 MHz crystal, and produces multiple output

clocks for networking chips, PCI devices, SDRAM, and

ASICs.

PIN CONFIGURATION

FREQUENCY TABLE

FS0

FS1

SDRAM

FS2

Pin 14

0

0

0

25MHz

0

1

M

Disable

1

0

1

1

1

SST: SST modulation applied

BLOCK DIAGRAM

XTAL

OSC

50MHz

(can be disabled)

XIN

XOUT

SDRAM (66.6, 75, 83.3, 100MHz)

25MHz/100 MHz

(can be disabled)

Control

Logic

FS (0:3)

4

1

1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VDD

VDD

25MHz/100MHz

GND

GND

SDRAMx2

VDD

XIN

XOUT/50MHz_OE*^

GND

VDD

50MHz/FS0*^

GND

50MHz/FS1*^

resistor *: Bi-directional pin (input value is latched upon power-up).