AT25SF081B datasheet(48/61 Pages) DIALOG

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Datasheet

5-Aug-2021

DS-AT25SF081B-189

Revision E

8-Mbit SPI Serial Flash Memory

with Dual-I/O and Quad-I/O Support

AT25SF081B

Datasheet

12.5 DEEP POWER-DOWN (B9H)

During normal operation, the device is placed in Standby Mode to consume less power as long as the CS pin remains deasserted

and no internal operation is in progress. The Deep Power-Down command lets the device be put into an even lower-power

consumption state, called the Deep Power-Down mode.

When the device is in the Deep Power-Down mode, all commands, including the Read Status Register command, are ignored,

with the exception of the Resume from Deep Power-Down command. Since all commands are ignored, the mode can be used

as an extra protection mechanism against program and erase operations.

Entering the Deep Power-Down mode is done by asserting the CS pin, clocking in the opcode of B9h, and then deasserting the

CS pin. Any additional data clocked into the device after the opcode is ignored. When the CS pin is deasserted, the device enters

the Deep Power-Down mode.

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary

(multiples of eight bits); otherwise, the device aborts the operation and returns to the Standby Mode once the CS pin is deasserted.

Also, the device defaults to the Standby Mode after a power-cycle.

The Deep Power-Down command is ignored if an internally self-timed operation, such as a program or erase cycle, is in progress.

The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the

device to enter the Deep Power-Down mode.

Figure 39: Deep Power-Down

SCK

MSB

ICC

10111001

OPCODE

High-Impedance

Standby Mode Current

Active Current

Deep Power-Down Mode Current

tEDPD

AT25SF081B Datasheet(PDF) 48 Page - Dialog Semiconductor