AT25SF161B datasheet(21/64 Pages) DIALOG

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Datasheet

21-Apr-2021

DS-AT25SF161B-188

Revision E

AT25SF161B

16-Mbit SPI Serial Flash Memory

with Dual I/O and Quad I/O Support

7.5.1 Quad-I/O Read Array (EBh) with Continuous Read Mode

The Read Quad I/O command can further reduce command overhead through setting the Continuous Read Mode bits (M7-0)

after the input Address bits (A23-0), as shown in Figure 12. The upper nibble (M7-4) of the Continuous Read Mode bits controls

the length of the next Fast Read Quad I/O command through the inclusion, or exclusion, of the first byte command code. The

lower nibble bits (M3-0) of the Continuous Read Mode bits are don't care. However, the IO pins must be high-impedance prior to

the falling edge of the first data out clock. If the Continuous Read Mode bits M5-4 = (1,0), the next Quad-I/O Read Array command

(after CS is raised and then lowered) does not require the EBh command code, as shown in Figure 13. This reduces the command

sequence by eight clocks and allows the Read address to be immediately entered after CS is asserted low. If the Continuous

Read Mode bits M5-4 do not equal to (1,0), the next command (after CS is raised and then lowered) requires the first byte

command code, thus returning to normal operation. A Continuous Read Mode Reset command can also be used to reset M7-0

before issuing normal commands.

Figure 13: Quad I/O Read Array with Continuous Read Mode (Previous Command Set M5, M4 = 1,0)

I/O0

(SI)

SCK

I/O1

(SO)

410 11

A20 A16 A12 A8

A23-A16 A15-A8

A21 A17 A13 A9

Byte 1

Byte 2

I/O2

(WP)

A22 A18 A14 A10

D2 D6

I/O3

(HOLD)

A23 A19 A15 A11

D3 D7

14 15

A4 A0 M4 M0

A7-A0

M7-M0

A6 A2 M6 M2

A7 A3 M7 M3

A5 A1 M5 M1

Dummy

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