AT25SF641B datasheet(20/59 Pages) DIALOG

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AT25SF641B

DS-AT25SF641B–191D–12-2020

7.6

Quad-I/O Word Fast Read (E7h)

The Quad-I/O Word Fast Read instruction is similar to the Quad Fast Read instruction, except that the lowest

address bit (A0) must equal 0 and have two dummy clock cycles. Figure 7-10 shows the instruction sequence; the

first byte addressed can be at any location. The address is automatically incremented to the next higher address

after each byte of data is shifted out. The Quad Enable bit (QE) of the Status Register (S9) must be set to enable.

Figure 7-10. Quad-I/O Word Fast Read Timing (Initial Command Set M5, M4 ≠ 1,0) SPI Mode

7.6.1

Quad-I/O Word Fast Read with “Continuous Read Mode”

The Quad-I/O Word Fast Read instruction can further reduce instruction overhead by setting the “Continuous Read

Mode” bits (M7-0) after input of the Address bits (A23-0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), the

next Quad-I/O Fast Read instruction (after CS is raised and then lowered) does not require the E7h instruction

code. Figure 7-11 shows the instruction sequence. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0),

the next instruction requires the first E7h instruction code, thus returning to normal operation. A “Continuous Read

Mode” Reset command also can be used to reset (M5-4) before issuing normal command.

Figure 7-11. Quad-I/O Word Fast Read Timing (Previous Command Set M5, M4 = 1,0) SPI Mode

410 11

14 15

19 20

Dummy

Byte 1

Byte 2

Byte 3

M7-M0

A7-A0

A15-A8

A23-A16

A20

A16

A12

11100111

A21

A17

A13

A22

A18

A14

A10

A23

A19

A15

A11

SCK

I/O

(SI)

(SO)

(WP)

(HOLD)

I/O0

(SI)

SCK

I/O1

(SO)

410 11

A20 A16 A12 A8

A23-A16 A15-A8

A21 A17 A13 A9

Byte 1

Byte 2

I/O2

(WP)

A22 A18 A14 A10

D2 D6

I/O3

(HOLD)

A23 A19 A15 A11

D3 D7

14 15

A4 A0 M4 M0

A7-A0

M7-M0

A6 A2 M6 M2

A7 A3 M7 M3

A5 A1 M5 M1

Dummy

D4 D0

Byte 3

D6 D2

D7 D3

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