K6F2016R4G datasheet(9/10 Pages) SAMSUNG

Part #	K6F2016R4G

Description	2Mb(128K x 16 bit) Low Power SRAM

PDF	10 Pages

Scroll/Zoom	100%

Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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9 / 10 page

Revision 0.0

CMOS SRAM

April 2005

K6F2016R4G Family

- 9 -

Preliminary

Address

Data Valid

UB, LB

Data in

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition

when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

tAS(3)

DATA RETENTION WAVE FORM

CS or LB/UB controlled

VCC

1.65V

1.4V

VDR

CS or LB/UB

GND

Data Retention Mode

≥VCC-0.2V or LB=UB≥Vcc-0.2V

tSDR

tRDR

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