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DA9070

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.3

13-Oct-2020

60 of 130

The RESET behavior is configurable with the options shown in Table 41.

Table 41: RIN_N Reset Timer Configuration

Configuration Description

RIN_N_RST_REC

0x10 [1:0]

0: RESET event has no effect

1: Enter ship mode at RESET

2: Enter Hi-Z mode at RESET

PWR_CYC_MODE

0x12 [1]

0: Power-cycle triggered by VDD_PWR insertion / removal

1: Power-cycle triggered by RESET timer when VDD_PWR present

RIN_N_RST_ROUT_EN

0x10 [3:2]

0: Disable ROUT_N toggle at RESET

1: Enable ROUT_N toggle at RESET

2: Enable ROUT_N toggle at RESET only when VDD_PWR is present

The RIN_N timer can also be used to exit Ship mode. A WAKE1 event will trigger Ship mode exit,

with WAKE2 and RESET being ignored.

If ROUT_N is enabled, a RESET event will cause the ROUT_N output to toggle low for 400 msec

(typ). ROUT_N is an open-drain output that should be pulled-up to the logic rail with a 1 k

 to 100 k

resistor.

9.8.5

System Status Register

The System Status register (0x02) indicates the status of five system functions:

•

BUCK: High = enabled with no faults

•

BOOST: High = enabled with no faults

•

Charge Status: Ready, Charge in Progress, Charge Done, or Fault

•

MODE: Logic state of the MODE pin

•

Power-Cycle: High indicates that a power-cycle has occurred

Only the power-cycle bit shows previous events and is read-clear. The others are READ only,

reflecting the current status.

9.8.6

I2C Programming

The DA9070 includes an I2C compatible interface which allows READ/WRITE access to all registers.

The interface is disabled in some modes and is configurable as described in Table 42.

Table 42: I2C Interface Configuration

I2C_HIZ_EN

0x15 [0]

Ship mode

Hi-Z mode

Active battery mode

Charge mode

disabled

active

disabled

active

I2C communication uses the SDA and SCL are open drain I/O pins. These should be pulled up to

VDDIO with a 1k

 to 100k resistor. SCL is the serial clock generated by the host and SDA is the

serial address and data input/output.

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