IMX6SDLCEC datasheet(6/169 Pages) NXP

6 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Introduction

— 32 KByte L1 Instruction Cache

— 32 KByte L1 Data Cache

— Private Timer and Watchdog

— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor

The Arm Cortex-A9 MPCore complex includes:

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General Interrupt Controller (GIC) with 128 interrupt support

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Global Timer

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Snoop Control Unit (SCU)

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512 KB unified I/D L2 cache:

— Used by one core in i.MX 6Solo

— Shared by two cores in i.MX 6DualLite

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Two Master AXI bus interfaces output of L2 cache

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Frequency of the core (including NEON and L1 cache), as per Table 8.

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NEON MPE coprocessor

— SIMD Media Processing Architecture

— NEON register file with 32x64-bit general-purpose registers

— NEON Integer execute pipeline (ALU, Shift, MAC)

— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

— NEON load/store and permute pipeline

The SoC-level memory system consists of the following additional components:

— Boot ROM, including HAB (96 KB)

— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)

— Secure/non-secure RAM (16 KB)

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External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume,

cost effective handheld DRAM, NOR, and NAND Flash memory standards.

— 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and DDR3L-800 in i.MX 6Solo; 16/32/64-bit

LP-DDR2-800, 16/32/64-bit DDR3-800 and DDR3L-800, supporting DDR interleaving mode

for 2x32 LPDDR2-800 in i.MX 6DualLite

— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,

BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.

— 16/32-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces.

— 16/32-bit PSRAM, Cellular RAM

Each i.MX 6Solo/6DualLite processor enables the following interfaces to external devices (some of them

are muxed and not available simultaneously):

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Displays—Total of five interfaces available. Total raw pixel rate of all interfaces is up to 450

Mpixels/sec, 24 bpp. Up to two interfaces may be active in parallel (excluding EPDC).

— One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual

HD1080 and WXGA at 60 Hz)

IMX6SDLCEC Datasheet(PDF) 6 Page - NXP Semiconductors

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