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DA9220 Datasheet(PDF) 18 Page - Dialog Semiconductor |
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DA9220 Datasheet(HTML) 18 Page - Dialog Semiconductor |
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18 / 62 page ![]() DA9220 High-Performance Dual-Channel DC-DC Converter Datasheet Revision 2.1 17-Sep-2020 CFR0011-120-00 18 of 62 © 2020 Dialog Semiconductor 4 Functional Description 4.1 DC-DC Buck Converter DA9220 contains two buck converters, Buck1 and Buck2, each capable of delivering up to 3 A output current at a 0.3 V to 1.9 V output voltage range. Buck1 and Buck2 have two voltage registers each. One defines the normal output voltage, while the other offers an alternative retention voltage. In this way, different application power modes can easily be supported. The voltage selection can be operated either via GPI or via control interface to guarantee the maximum flexibility according to the specific host processor status in the application. When a buck is enabled, its output voltage is monitored and a power good signal indicates that the buck output voltage has reached a level higher than the VTHR_PG_RISE threshold. The power good status is lost when the voltage drops below VTHR_PG_DWN or increases above VTHR_HV. For each of the buck converters the status of the power good indicator can be read back via I2C from the PG1 and PG2 status bits. It can be also individually assigned to any of the GPIOs by setting the GPIO mode registers to either PG1 or PG2 output. The buck converters are capable of supporting DVC transitions that occur: ● When the active and selected A- or B-voltage is updated to a new target value. ● When the voltage selection is changed from the A- to B-voltage (or B- to A-voltage) using CH<x>_VSEL. The DVC controller operates in pulse width modulation (PWM) mode with synchronous rectification. The slew rate of the DVC transition is individually programmed for each buck converter at 10 mV per 8 µs, 4 µs, 2 µs, 1 µs, or 0.5 µs in register bits CH1_SR_DVC and CH2_SR_DVC. A pull- down resistor (typically 150 Ω) for each phase is always activated unless it is disabled by setting register bits CH<x>_PD_DIS to 1. 4.1.1 Switching Frequency The buck switching frequency can be tuned using register bit OSC_TUNE. The internal 8 MHz oscillator frequency is tuned in ±160 kHz steps. This impacts the buck converter frequency in steps of 80 kHz and helps to mitigate possible disturbances to other high frequency systems in the application. 4.1.2 Operation Modes and Phase Selection The buck converters can operate in PWM and PFM modes. The operating mode is selected using register bits CH1_<A or B>_MODE and CH2_<A or B>_MODE. If the automatic operation mode is selected on CH1_<A or B>_MODE or CH2_<A or B>_MODE, the buck converters automatically change between synchronous PWM mode and PFM depending on the load current. This improves the efficiency across the whole range of output load currents. |
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