IMX7ULPCECB2 datasheet(30/122 Pages) NXP

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5.1 JTAG—system control

Joint Test Action Group Controller (JTAGC) provides the means to test chip

functionality and connectivity while remaining transparent to system logic when not in

test mode. Testing is performed via a boundary scan technique, as defined in the IEEE

1149.1-2001 standard.

5.2 JTAG device identification register

The device identification register (JTAG ID) allows the revision number and part

number to be read through the TAP. See the device identification register section of the

i.MX 7ULP Applications Processor Reference Manual

for details. This table shows the

Part Identification Number (PIN) and the Part Revision Number (PRN) for each i.MX

7ULP silicon revision.

Table 3. JTAG device identification register information

Silicon Revision

Part Identification Number (PIN)

Part Revision Number (PRN)

10'b0011100001

4’b0000

10'b0011100001

4’b0001

10'b0011100001

4’b0010

10'b0011100001

4’b0011

The contents of the JTAD ID register are also mirrored in a SIM register called

JTAG_ID_REG (address 0x410A_308C).

5.3 Oscillators and PLLs

5.3.1 System oscillator (SYS OSC)

The system oscillator (SYS OSC) is a crystal oscillator. The SYS OSC, in conjunction

with an external crystal or resonator, generates a reference clock for this chip. It also

provides the option for an external input clock to EXTAL signal directly.

System control modules

i.MX 7ULP Applications Processor—Consumer, Rev. 0, 09/2020

NXP Semiconductors

IMX7ULPCECB2 Datasheet(PDF) 30 Page - NXP Semiconductors