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PCIMX6D4AVT08AC Datasheet(PDF) 13 Page - NXP Semiconductors |
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PCIMX6D4AVT08AC Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 162 page  Modules List i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 13 MMDC Multi-Mode DDR Controller Connectivity Peripherals DDR Controller has the following features: • Supports 16/32/64-bit DDR3 / DDR3L or LPDDR2 • Supports both dual x32 for LPDDR2 and x64 DDR3 / LPDDR2 configurations (including 2x32 interleaved mode) • Supports up to 4 GByte DDR memory space OCOTP_CTRL OTP Controller Security The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals, requiring permanent non-volatility. OCRAM On-Chip Memory Controller Data Path The On-Chip Memory controller (OCRAM) module is designed as an interface between system’s AXI bus and internal (on-chip) SRAM memory module. In i.MX 6Dual/6Quad processors, the OCRAM is used for controlling the 256 KB multimedia RAM through a 64-bit AXI bus. OSC 32 kHz OSC 32 kHz Clocking Generates 32.768 kHz clock from an external crystal. PCIe PCI Express 2.0 Connectivity Peripherals The PCIe IP provides PCI Express Gen 2.0 functionality. PMU Power-Management Functions Data Path Integrated power management unit. Used to provide power to various SoC domains. PWM-1 PWM-2 PWM-3 PWM-4 Pulse Width Modulation Connectivity Peripherals The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound. RAM 16 KB Secure/non-secure RAM Secured Internal Memory Secure/non-secure Internal RAM, interfaced through the CAAM. RAM 256 KB Internal RAM Internal Memory Internal RAM, which is accessed through OCRAM memory controllers. ROM 96 KB Boot ROM Internal Memory Supports secure and regular Boot Modes. Includes read protection on 4K region for content protection ROMCP ROM Controller with Patch Data Path ROM Controller with ROM Patch support SATA Serial ATA Connectivity Peripherals The SATA controller and PHY is a complete mixed-signal IP solution designed to implement SATA II, 3.0 Gbps HDD connectivity. Table 2. i.MX 6Dual/6Quad Modules List (continued) Block Mnemonic Block Name Subsystem Brief Description |
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