84025EM

www.icst.com/products/hiperclocks.html

REV. A APRIL 16, 2003

9

Integrated

Circuit

Systems, Inc.

ICS84025

PRELIMINARY

The following component footprints are used in this layout

example:

All the resistors and capacitors are size 0603.

Place the decoupling capacitors as close as possible to the power

pins. If space allows, placement of the decoupling capacitor on

the component side is preferred. This can reduce unwanted in-

ductance between the decoupling capacitor and the power pin

caused by the via.

Maximize the power and ground pad sizes and number of vias

capacitors. This can reduce the inductance between the power

and ground planes and the component power and ground pins.

The RC filter consisting of R7, C11, and C16 should be placed

as close to the V

Poor signal integrity can degrade the system performance or

cause system failure. In synchronous high-speed digital systems,

the clock signal is less tolerant to poor signal integrity than other

signals. Any ringing on the rising or falling edge or excessive ring

back can cause system failure. The shape of the trace and the

trace delay might be restricted by the available space on the board

and the component location. While routing the traces, the clock

signal traces should be routed first and should be locked prior to

routing other signal traces.

• The differential 50

Ω output traces should have the

same length.

• Avoid sharp angles on the clock trace. Sharp angle

turns cause the characteristic impedance to change on

the transmission lines.

• Keep the clock traces on the same layer. Whenever pos-

sible, avoid placing vias on the clock traces. Placement

of vias on the traces can affect the trace characteristic

impedance and hence degrade signal integrity.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow a separation of at least three trace

widths between the differential clock trace and the other

signal trace.

• Make sure no other signal traces are routed between the

clock trace pair.

• The matching termination resistors should be located as

close to the receiver input pins as possible.

The crystal X1 should be located as close as possible to the pins

21 (XTAL1) and 20 (XTAL2). The trace length between the X1

and U1 should be kept to a minimum to avoid unwanted parasitic

inductance and capacitance. Other signal traces should not be

routed near the crystal traces.

VDD

VIA

C1

R7

50 Ohm traces

PIN1

R3

R5

R2

R1

C7

GND

C4

C2

50 Ohm traces

C3

C16

C11

C5

R6

X1

C6

VDDA

R4

50 Ohm traces

50 Ohm traces

50 Ohm traces

50 Ohm traces

U1