ICS843011CGLF datasheet(5/11 Pages) ICST

5 / 11 page

843011CG

www.icst.com/products/hiperclocks.html

REV. A JANUARY 25, 2006

Integrated

Circuit

Systems, Inc.

ICS843011C

FEMTOCLOCKS™ CRYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

APPLICATION INFORMATION

Figure 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS843011C has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2 below were determined using a 26.5625MHz, 18pF

parallel resonant crystal and were chosen to minimize the

ppm error. The optimum C1 and C2 values can be slightly

adjusted for different board layouts.

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS843011C provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

CC and VCCA

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10

Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each V

CCA pin.

POWER SUPPLY FILTERING TECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

CCA

μF

.01

μF

3.3V

.01

μF

33p

18pF Parallel Crystal

22p

XTAL_OUT

XTAL_IN

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