NAND01G-N datasheet(13/23 Pages) STMICROELECTRONICS

13 / 23 page

NAND01G-N

Signals description

Rev1.0

13/23

2.6

Flash memory Read Enable (R)

The NAND Flash memory Read Enable pin, R, controls the sequential data output during

Read operations. The falling edge of R also increments the internal column address counter

by one.

2.7

Flash memory Write Enable (WF)

The NAND Flash memory Write Enable input, W, controls writing to the Command Interface,

Input Address and Data latches. Both addresses and data are latched on the rising edge of

Write Enable.

2.8

Flash memory Write Protect (WP)

The Write Protect pin is a NAND Flash memory input that gives a hardware protection

against unwanted program or erase operations. When Write Protect is Low, VIL, the NAND

Flash memory device does not accept any program or erase operations.

It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.

2.9

Flash memory Ready/Busy (RB)

The Ready/Busy output, RB, is an open-drain NAND Flash memory output that can be used

to identify if the P/E/R Controller is currently active.

When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the

operation completes Ready/Busy goes High, VOH.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

2.10

Flash memory VDDF supply voltage

VDDF provides the power supply to the internal core of the NAND Flash memory device. It is

the main power supply for all operations (read, program and erase).

2.11

Flash memory VSSF ground

Ground, VSSF, is the reference for the power supply for the NAND Flash memory. It must be

connected to the system ground.

NAND01G-N Datasheet(PDF) 13 Page - STMicroelectronics