MCIMX6DP4EYM2AB datasheet(39/168 Pages) NXP

39 / 168 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an

input or output.

Figure 3. Circuit for Parameters Voh and Vol for I/O Cells

4.6.1

XTALI and RTC_XTALI (Clock Inputs) DC Parameters

Table 21 shows the DC parameters for the clock inputs.

NOTE

The Vil and Vih specifications only apply when an external clock source is

used. If a crystal is used, Vil and Vih do not apply.

4.6.2

General Purpose I/O (GPIO) DC Parameters

Table 22 shows DC parameters for GPIO pads. The parameters in Table 22 are guaranteed per the

operating ranges in Table 6, unless otherwise noted.

Table 21. XTALI and RTC_XTALI DC Parameters

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

XTALI high-level DC input voltage

Vih

—

0.8 x NVCC_PLL_OUT — NVCC_PLL_ OUT V

XTALI low-level DC input voltage

Vil

—

0.2

RTC_XTALI high-level DC input

voltage

Vih

—

0.8

—

1.1(See note 1)

1 This voltage specification must not be exceeded and, as such, is an absolute maximum specification.

RTC_XTALI low-level DC input

voltage

Vil

—

0.2

Input capacitance

CIN

Simulated data

—

XTALI input leakage current at

startup

IXTALI_STARTUP Power-on startup for

0.15 msec with a driven

24 MHz clock

at 1.1 V. 2

2 This current draw is present even if an external clock source directly drives XTALI.

—

600

μA

DC input current

IXTALI_DC

——

—

2.5

μA

Predriver

pdat

ovdd

pad

nmos (Rpd)

ovss

Voh min

Vol max

pmos (Rpu)

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