EZ80F92 datasheet(21/266 Pages) ZILOG

21 / 266 page

PS015309-1004

PRELIMINARY

Architectural Overview

eZ80F92/eZ80F93

Product Specification

ADDR11

Address Bus

Bidirectional

Configured as an output in normal

operation. The address bus selects a

location in memory or I/O space to be read

or written. Configured as an input during

bus acknowledge cycles. Drives the Chip

Select/Wait State Generator block to

generate Chip Selects.

ADDR12

Address Bus

Bidirectional

Configured as an output in normal

operation. The address bus selects a

location in memory or I/O space to be read

or written. Configured as an input during

bus acknowledge cycles. Drives the Chip

Select/Wait State Generator block to

generate Chip Selects.

ADDR13

Address Bus

Bidirectional

Configured as an output in normal

operation. The address bus selects a

location in memory or I/O space to be read

or written. Configured as an input during

bus acknowledge cycles. Drives the Chip

Select/Wait State Generator block to

generate Chip Selects.

ADDR14

Address Bus

Bidirectional

Configured as an output in normal

operation. The address bus selects a

location in memory or I/O space to be read

or written. Configured as an input during

bus acknowledge cycles. Drives the Chip

Select/Wait State Generator block to

generate Chip Selects.

VDD

Power Supply

Power Supply.

VSS

Ground

Ground.

ADDR15

Address Bus

Bidirectional

Configured as an output in normal

operation. The address bus selects a

location in memory or I/O space to be read

or written. Configured as an input during

bus acknowledge cycles. Drives the Chip

Select/Wait State Generator block to

generate Chip Selects.

Table 2. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued)

Pin #

Symbol

Function

Signal Direction

Description

EZ80F92 Datasheet(PDF) 21 Page - Zilog, Inc.

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