SST26VF040A-80ISLASHSNVAO datasheet(15/73 Pages) MICROCHIP

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DS20006292B-page 15

SST26VF040A

5.1

No Operation (NOP)

The No Operation command only cancels a Reset

Enable command. NOP has no impact on any other

command.

5.2

Reset Enable (RSTEN) and Reset

(RST)

The Reset operation is used as a system (software)

Reset that puts the device in normal operating Ready

mode. This operation consists of two commands:

Reset Enable (RSTEN) followed by Reset (RST).

To reset SST26VF040A, the host drives CE# low,

sends the Reset Enable command (66H), and drives

CE# high. Next, the host drives CE# low again, sends

the Reset command (99H), and drives CE# high, see

Figure 5-1.

The Reset operation requires the Reset Enable

command followed by the Reset command. Any

command other than the Reset command after the

Reset Enable command will disable the Reset Enable.

Once the Reset Enable and Reset commands are

successfully executed, the device returns to normal

operation Read mode and then does the following:

resets the protocol to SPI mode, resets the burst length

to 8 bytes, clears BUSY bit and WEL bit in the STATUS

WSE bit and WSP bit in the Configuration register to its

default state. A device Reset during an active program

or erase operation aborts the operation, which can

cause the data of the targeted address range to be

corrupted or lost. Depending on the prior operation, the

Reset timing may vary. Recovery from a write operation

requires more latency time than recovery from other

operations. See Table 8-2 for Reset timing parameters.

Power-Saving

DPD

Deep Power-Down

Mode

B9H

104 MHz/80 MHz

RDPD

Release from Deep

Power-Down and

Read ID

ABH

1 to

∞

Note 1:

Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode.

Address bits above the Most Significant bit of each density can be VIL or VIH.

Address, Dummy/Mode bits, and data cycles are two clock periods in SQI and eight clock periods in SPI mode.

The maximum frequency for all instructions is up to 104 MHz from 2.7V-3.6V and up to 80 MHz from 2.3V-3.6V

unless otherwise noted. For extended temperature (125°C) the maximum frequency is up to 80 MHz.

The Read STATUS register is continuous with ongoing clock cycles until terminated by a low-to-high transition

on CE#.

Data cycles are four clock periods.

The maximum frequency for SDIOR is up to 80 MHz from 2.3V-3.6V.

Address, Dummy/Mode bits, and data cycles are four clock periods.

Data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.

10: Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the

command.

11: 4-Kbyte Sector Erase addresses: use AMS-A12, remaining addresses are “don’t care” but must be set either at

VIL or VIH.

12: 32-Kbyte Block Erase addresses: use AMS-A15, remaining addresses are “don’t care” but must be set either at

VIL or VIH.

13: 64-Kbyte Block Erase addresses: use AMS-A16, remaining addresses are “don’t care” but must be set either at

VIL or VIH.

TABLE 5-1:

DEVICE OPERATION INSTRUCTIONS (CONTINUED)

Instruction

Description

Code

Cycle(1)

Mode

Address

Cycle(s)(2,3)

Dummy

Cycle(s)(3)

Data

Cycle(s)(3)

Maximum

Frequency (4)

SPI

SQI

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