Z8623012SSC datasheet(21/61 Pages) ZILOG

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I2C BUS OPERATION

SERIAL COMMUNICATIONS INTERFACE

PS000400-TVC0499

Z86230—PRELIMINARY

All READ sequences output the SSR ﬁrst. If the Serial Status register DAV bit is

set, a 2- or multiple-byte READ sequence can be initiated, beginning with a

START

condition. If the DAV bit is not set, the I2C master device should not

attempt to read any data bytes or the required data can be lost from the Z86230

output registers. The I2C master device should end the READ sequence by failing

to acknowledge the received byte. This sequence is repeated until the DAV bit

becomes true.

NOTE:

In all

I2C READ operations (1-, 2- and 3-byte reads are illustrated in Figure 5), the

most recent byte read from the Z86230 should be acknowledged by the master with a Not

Acknowledge (

NACK). The DAV bit of the Serial Status Register (SSR) is cleared by the

master clocking out the eighth bit of the first data byte read. The

DAV bit is never cleared

by just reading the

SSR (One Byte READ) alone. All data is output MSB first.

The master’s sequence for reading two data bytes (total of 3 bytes including SSB)

from the Z86230 is:

Start

Slave_Address_Read/Slave_ACK

SS_Byte/Master ACK

First_Byte/Master ACK

Second_Byte/Master_NACK

Stop

4.1.5 Clock and Data Transitions

The SCLK and SDA bus lines are normally pulled High with a resistor. Data on the

SDA

bus may only change during SCLK Low time periods. Data changes during

SCLK

High periods indicate a START or STOP condition as deﬁned in Table 6.

4.1.6 START Condition

A High-to-Low transition of SDA with SCLK High is a START condition which

must precede any other command.

FIGURE 5. I2C BUS READ (COMMAND)

NOTE: In all I

2C READ operations, the most recent byte read from the Z86230 must be

acknowledged by the master with a NACK (Not ACKnowledge).

START

STOP

SLAVE ADDR

SERIAL STATUS

(READ=29h for the 1st I2C Address and 2Bh for the 2nd I2C Address)

START

STOP

SLAVE ADDR

SERIAL STATUS

(READ=29h for the 1st I2C Address and 2Bh for the 2nd I2C Address)

READ DATA1

START

STOP

SERIAL STATUS

(READ=29h for the 1st I2C Address and 2Bh for the 2nd I2C Address)

READ DATA1

READ DATA2

I2C Two-Byte READ (Status & Data1)

I2C Three-Byte READ (Status, Data1, & Data2)

SLAVE ADDR

I2C One-Byte READ (Status Only)

NACK

Z8623012SSC Datasheet(PDF) 21 Page - Zilog, Inc.

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