MAX4397DACTM datasheet(13/30 Pages) MAXIM

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Video Outputs

The DC level at the video outputs is controlled so that

coupling capacitors are not required, and all of the video

outputs are capable of driving a DC-coupled, 150Ω,

back-terminated coax load with respect to ground.

In a typical television input circuit (see Figure 3), the

video output driver on the SCART chip only needs to

source current. Users should note that, while the

SCART specification states 75Ω impedance, in prac-

tice, typical SCART chip implementations assume 75Ω

input resistance to ground (and source current from the

video output stage).

Since some televisions and VCRs use the horizontal

sync height for automatic gain control, the

MAX4397DA/SA accurately reproduce the sync height

to within ±2%.

Slow Switching

The MAX4397DA/SA support the IEC 933-1,

Amendment 1, tri-level slow switching that selects the

aspect ratio for the display (TV). Under I2C-compatible

control, the MAX4397DA/SA set the slow-switching out-

put voltage level. Table 1 shows the valid input levels of

the slow-switching signal and the corresponding oper-

ating modes of the display device.

Two bidirectional ports are available for slow-switching

signals for the TV and VCR. The slow-switching input

status is continuously read and stored in the register

0Eh. The slow-switching outputs can be set to a logic

level or high impedance by writing to registers 07h and

09h. See Tables 8 and 10 for details.

Fast Switching

The VCR or MPEG decoder outputs a fast-switching

signal to the display device or TV to insert an on-screen

display (OSD). The fast-switching signal can also be

set to a constant high or low output signal through the

I2C interface. The fast-switching output can be set

through writing to register 07h.

Y/C Mixer

The MAX4397DA/SA include an on-chip mixer to pro-

duce Composite video (CVBS) when S-video (Y and C)

is present. The Composite video drives the

RF_CVBS_OUT output pin. The circuit sums Y and C

signals to obtain the CVBS component. A +6dB output

buffer drives RF_CVBS_OUT.

Video Reconstruction Filter

The encoder DAC outputs need to be lowpass-filtered

to reject the out-of-band noise. The MAX4397DA/SA

integrate the reconstruction filter. The filter is fourth

order, which is composed of two Sallen-Key biquad in

cascade, implementing a Butterworth-type transfer

function. The internal reconstruction filters feature a

5.5MHz cutoff frequency and -30dB minimum attenua-

tion at 27MHz. Note that the SET pin is used to set the

accuracy of the filter cutoff frequency. Connect a

100kΩ resistor from SET to ground.

SCART Audio Switching

Audio Inputs

All audio inputs for the MAX4397SA are single-ended

and AC-coupled. The MAX4397DA audio inputs are

singled-ended and AC-coupled except for the audio

encoder input, which is differential DC-coupled.

The audio block has three stereo audio inputs from the

TV, the VCR, and the MPEG decoder SCART. Each

input has a 100kΩ resistor connected to an internally

generated voltage equal to 0.23 x V12, except for the

encoder input of the MAX4397DA, where the DC bias is

fixed externally.

Audio/Video Switch for Dual SCART Connectors

______________________________________________________________________________________

Table 1. Slow-Switching Modes

SLOW-SWITCHING

SIGNAL VOLTAGE

(V)

MODE

0 to 2

Display device uses an internal source

such as a built-in tuner to provide a

video signal

4.5 to 7.0

Display device uses a video signal from

the SCART connector and sets the

display to a 16:9 aspect ratio

9.5 to 12.6

Display device uses a signal from the

SCART connector and sets the display

to a 4:3 aspect ratio

MAX4397DA/SA

SET-TOP BOX

+5V

VIDEO

OUTPUT

RESTORE

SCART

CABLE

0.1µF

5kΩ

75Ω

INPUT

TERMINATION

RESISTOR

75Ω

BACK

TERMINATION

RESISTOR

Figure 3. Typical TV Input Circuit

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