PD70224 datasheet(16/31 Pages) MICROCHIP

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Pin Number

PD70101 Pin

Name

PD70201 Pin Name Description

VINS

VPP input voltage sensing for UVLO comparator. Connect

to an external resistor divider from VPP to GND. Threshold

is 1.2 V reference.

HYST

Output of the VINS/UVLO comparator. This pin is used for

VPP UVLO hysteresis programming.

SYNC

External Clock synchronization for the DC-DC controller.

Connect an external clock as defined in the EC table to this

pin to synchronize the DC-DC converter switching

frequency to this clock. PG rising edge is synchronized with

the clock rising edge.

RFREQ

DC-DC Switching Frequency Setting. Connect a resistor

from this pin to GND to set the switching frequency.

Soft-start: Connect a capacitor from this pin to GND to set

the soft-start time of the DC-DC converter. This capacitor is

charged with an internal current source to 1.2 V.

RCLP

Low Power Mode Clamp. Connect a resistor from this pin to

GND to program the LPM clampimg voltage or connect this

pin to GND to disable LPM.

VSN

Differential Amplifier's negative input. Connect this to the

junction of a resistor divider from Vo- to GND for the Direct

Buck converter application.

VSP

Differential Amplifier's positive input. Connect this to the

junction of a resistor divider from Vo+ to GND for the Direct

Buck converter application.

COMP

Error Amplifier Output. Short to FB pin when driven directly

with an optoisolator for Isolated DC-DC Converter. Connect

to FB via RC compensation networks for Non-Isolated

Direct Buck Converter.

DAO

Differential Amplifier Output. Connect to FB (externally) for

Non-Isolated Direct Buck Converter.

Inverting Input of the Error Amplifier. Connect to opto-

coupler for Isolated DC-DC. Connect to RC compensation

networks for Non-isolated DC-DC.

GND

This is Analog GND. Connect to a local AGND plane. Soft-

start capacitor and the frequency setting resistor return to

this local GND plane.

5 V (GND reference) internal LDO Output. Connect a 1 µF

or higher ceramic cap from VL to GND.

Secondary Gate Driver. Output is the compliment of PG

output. Leave open (NC) if not used. SG is low when in Low

Power Skip Mode.

PGND

This is the Power Ground. Connect to a local PGND plane.

Input, VCC decoupling capacitors, PG and SG drivers.

Primary current sense resistor return to this PGND.

PD70101 and PD70201

Pin Configuration

Datasheet

DS00003738A-page 16

PD70224 Datasheet(PDF) 16 Page - Microchip Technology

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