PI6C48533-01LE datasheet(2/7 Pages) PERICOM

2 / 7 page

PI6C48533-01

3.3V Low Skew 1-to-4

Differential/LVCMOS to LVPECL Fanout Buffer

PS8737B

02/08/06

Pin Description

Name

Pin #

Type

Description

VEE

Connect to Negative power supply

CLK_EN

I_PU

Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx

outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 50KΩ pull-up.

CLK_

SEL

I_PD

Clock select input. When high, selects PCLK input. When low, selects CLK input. LVCMOS/

LVTTL level with 50KΩ pull-down.

CLK

I_PD

Non-inverting differential clock input

nCLK

I_PU

Inverting differential clock input

PCLK

I_PD

Non-inverting differential clock input

nPCLK

I_PU

Inverting differential clock input

8, 9

Not connected

VCC

10, 13,

Connect to 3.3V.

Q3, nQ3

11, 12

Differential output pair, LVPECL interface level.

Q2, nQ2

14, 15

Differential output pair, LVPECL interface level.

Q1, nQ1

16, 17

Differential output pair, LVPECL interface level.

Q0, nQ

19, 20

Differential output pair, LVPECL interface level.

Note:

1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up

Pin Characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

CIN

Input Capacitance

R_pullup

Input Pullup Resistance

KΩ

R_pulldown

Input Pulldown Resistance

Control Input Function Table(1)

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Source

Q0:Q3

nQ0:nQ3

CLK, nCLK

Diasbled: Low

Diasbled: High

PCLK, nPCLK

Disabled: Low

Disabled: High

CLK, nCLK

Enabled

PCLK, nPCLK

Enabled

Note:

1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.

PI6C48533-01LE Datasheet(PDF) 2 Page - Pericom Semiconductor Corporation

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