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LTC4282 Datasheet(PDF) 21 Page - Analog Devices |
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LTC4282 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 32 page ![]() LTC4238 21 Rev. 0 For more information www.analog.com (b) Normal Start-Up Waveform (c) Start-Up into Short-Circuit the cost of MOSFETs to achieve a given load current and RDS(ON). However, LSSS mode has limited capability to ride through an input step or a sustained load surge in current limit. Due to the low start-up current it also cannot start up a large resistive load such as a heating element or incandescent lamp. Figure 6a shows an application circuit for a 48V, 63A system operating in the low stress staged start mode. This mode is enabled by using configuration 5 or 6 in Table 3. In this mode GATE2 drives a compact, inexpen- sive MOSFET (M2) with small SOA as a trickle charging device for start-up. GATE1 drives parallel, low RDS(ON), APPLICATIONS INFORMATION Figure 6. Low Stress Staged Start Application (a) 48V, 63A Application Circuit 0.2m 4m RG1 10 M2 PSMN7R6-100BSE RG2 10 R1 360k 1% R3 93.1k 1% R2 3.01k 1% R1 4.22k 1% CTMR 180pF CFET 1.5µF R7 62k 1% R8 5.23k 1% CL CF 0.1µF RG3 10 C3 0.1µF RTOP1 59k 1% RBOTTOM1 44.2k 1% UV FLT# PG TMR VDD CONFIG1 SENSE1– SENSE1+ GATE1 SENSE2– GATE2 SOURCE VDSFB FB COMM LTC4238 SENSE2+ OV ISET CONFIG2 INTVCC TMRFET GND 48V GND BACKPLANE PLUG-IN BOARD RS1 RS2 SMC5K60A ×4 4238 F06a VOUT 48V 63A M1A M1B IPT015N10N5 IPT015N10N5 20ms/DIV 4238 F06b ∆VGATE2 10V/DIV ∆VGATE1 10V/DIV COMM 2V/DIV VOUT 50V/DIV FET-BAD TIMER EXPIRES 50ms/DIV 4238 F06c ∆VGATE1 10V/DIV ∆VGATE2 10V/DIV CURRENT 20A/DIV TMRFET 2V/DIV |
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