P87LPC779 datasheet(43/74 Pages) PHILIPS

43 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

43 of 74

9397 750 13213

8.14.2

Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and

TLn) are used. See Figure 20.

8.14.3

Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter (TL1) with automatic reload,

as shown in Figure 21. Overﬂow from TLn not only sets TFn, but also reloads TLn

with the contents of THn, which must be preset by software. The reload leaves THn

unchanged. Mode 2 operation is the same for Timer0 and Timer1.

8.14.4

Mode 3

When Timer1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0.

Timer0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic

for Mode 3 on Timer0 is shown in Figure 22. TL0 uses the Timer0 control bits: C/T,

GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine

cycles) and takes over the use of TR1 and TF1 from Timer1. Thus, TH0 now controls

the ‘Timer1’ interrupt.

Mode 3 is provided for applications that require an extra 8-bit timer. With Timer0 in

Mode 3, an P87LPC779 can look like it has three Timer/Counters. When Timer0 is in

Mode 3, Timer1 can be turned on and off by switching it into and out of its own Mode

3. It can still be used by the serial port as a baud rate generator, or in any application

not requiring an interrupt.

Table 34:

TCON - Timer/counter control register (address 88H) bit allocation

Bit addressable; Reset value: 00H

Bit

Symbol

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Table 35:

TCON - Timer/counter control register (address 88H) bit description

Bit

Symbol

Description

TF1

Timer1 overﬂow ﬂag. Set by hardware on Timer/Counter overﬂow.

Cleared by hardware when the interrupt is processed, or by

software.

TR1

Timer1 Run control bit. Set/cleared by software to turn

Timer/Counter 1 on/off.

TF0

Timer0 overﬂow ﬂag. Set by hardware on Timer/Counter overﬂow.

Cleared by hardware when the processor vectors to the interrupt

routine, or by software.

TR0

Timer0 Run control bit. Set/cleared by software to turn

Timer/Counter 0 on/off.

IE1

Interrupt 1 Edge ﬂag. Set by hardware when external interrupt 1

edge is detected. Cleared by hardware when the interrupt is

processed, or by software.

P87LPC779 Datasheet(PDF) 43 Page - NXP Semiconductors

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