SH7041A datasheet(345/923 Pages) RENESAS

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Channels 1, 2: TIER1, TIER2:

Bit:

TTGE

—

TCIEU

TCIEV

—

TGIEB

TGIEA

Initial value:

R/W:

R/W

Channels 3, 4: TIER3, TIER4:

Bit:

TTGE

—

TCIEV

TGIED

TGIEC

TGIEB

TGIEA

Initial value:

R/W:

R/W

• Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an

A/D conversion start request by a TGRA register input capture/compare-match.

Bit 7: TTGE

Description

Disable A/D conversion start requests (initial value)

Enable A/D conversion start request generation

• Bit 6—Reserved: This bit is reserved. It always reads as 0, and cannot be modified.

• Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests when the

underflow flag (TCFU) of the channel 1, 2 timer status register (TSR) is set to 1.

This bit is reserved for channels 0, 3, and 4. It always reads as 0. The write value should

always be 1.

Bit 5: TCIEU

Description

Disable UDF interrupt requests (TCIU) (initial value)

Enable UDF interrupt requests (TCIU)

• Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the

overflow flag TCFV of the timer status register (TSR) is set to 1.

Bit 4: TCIEVDescription

Disable TCFV interrupt requests (TCIV) (initial value)

Enable TCFV interrupt requests (TCIV)

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