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SH7041A Datasheet(PDF) 393 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 393 Page - Renesas Technology Corp

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355
Example of Complementary PWM Mode Setting Procedure: An example of the
complementary PWM mode setting procedure is shown in figure 12.38.
1.Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter
(TCNT) operation. Perform complementary PWM mode setting when TCNT3 and TCNT4 are
stopped.
2.Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2–TPSC0 and
bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2–CCLR0 to set
synchronous clearing only when restarting by a synchronous clear from another channel during
complementary PWM mode operation.
3.When performing brushless DC motor control, set bit BDC in the timer gate control register
(TGCR) and set the feedback signal input source and output chopping or gate signal direct
output.
4.Set the dead time in TCNT3.Set TCNT4 to H'0000.
5.Set only when restarting by a synchronous clear from another channel during complementary
PWM mode operation. In this case, synchronize the channel generating the synchronous clear
with channels 3 and 4 using the timer synchro register (TSYR).
6.Set the output PWM duty in the duty registers (TGR3B, TGR4A, TGR4B) and buffer registers
(TGR3D, TGR4C, TGR4D). Set the same initial value in each corresponding TGR.
7.Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle
data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus
the dead time in TGR3A and TGR3C.
8.Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE
in the timer output control register (TOCR), and set the PWM output level with bits OLSP and
OLSN.
9.Select complementary PWM mode in timer mode register 3 (TMDR3).Pins TIOC3A,
TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D function as output pins. Do not
set in TMDR4.
10.Set enabling/disabling of PWM waveform output pin output in the timer output master enable
register (TOER).
11.Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation.



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