SH7041A datasheet(439/923 Pages) RENESAS

439 / 923 page

401

TGR3A

TGR3C

TGR3B, TGR4A,

TGR4B

TGR3D, TGR4C,

TGR4D

H'0000

TIOC3A

TIOC3B

TIOC3D

TIOC4A

TIOC4C

TIOC4B

TIOC4D

TGF3C

TGF3D

TGF4C

TGF4D

TGR3A,

TGR3C

TGR3B, TGR3D,

TGR4A, TGR4C,

TGR4B, TGR4D

Buffer transfer with

compare match A3

TCNT3

Not set

Set

Point a

Point b

Figure 12.87 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode

• A mask operation

For A mask, the above operation is modified as follows:

When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of

TMDR4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of

TMDR4 is set to 1.

In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the

BFA and BFB bit settings of TMDR3. For example, if the BFA bit of TMDR3 is set to 1,

TGR3C functions as the buffer register for TGR3A. At the same time, TGR4C functions as the

buffer register for TRG4A.

When setting buffer operation for reset sync PWM mode, the compare-match flag TGFC bit

and TGFD bit operations will be the same for TSR3 and TSR4.

The TGFC bit and TGFD bit of TSR3 are not set when TGR3C and TGR3D are operating as

buffer registers. The TGFC bit and TGFD bit of TSR4 are not set when TGR4C and TGR4D

are operating as buffer registers.

SH7041A Datasheet(PDF) 439 Page - Renesas Technology Corp

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