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SH7041A Datasheet(PDF) 494 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 494 Page - Renesas Technology Corp |
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494 / 923 page  456 13.1.2 Block Diagram Figure 13.1 is the block diagram of the WDT. φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 φ/8192 Internal clock sources Clock Overflow Clock select Interrupt control Reset control RSTCSR TCSR: TCNT: RSTCSR: Timer control/status register Timer counter Reset control/status register TCNT TCSR Module bus Bus interface ITI (interrupt signal) WDTOVF Internal reset signal* WDT Note: * The internal reset signal can be generated by setting the register. The type of reset can be selected (power-on or manual). Figure 13.1 WDT Block Diagram 13.1.3 Pin Configuration Table 13.1 shows the pin configuration. Table 13.1 Pin Configuration Pin Abbreviation I/O Function Watchdog timer overflow WDTOVF O Outputs the counter overflow signal in the watchdog timer mode |
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