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SH7041A Datasheet(PDF) 521 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 521 Page - Renesas Technology Corp

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483
14.2.8
Bit Rate Register (BRR)
The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write the BRR. The BRR is initialized to H'FF by a power-on reset
or in standby mode. Each channel has independent baud rate generator control, so different values
can be set in the two channels. Manual reset does not initialize BRR.
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 14.3 lists examples of BRR settings in the asynchronous mode; table 14.4 lists examples of
BBR settings in the clock synchronous mode.
Table 14.3
Bit Rates and BRR Settings in Asynchronous Mode
φ (MHz)
Bit Rate
4
4.9152
6
(Bits/s)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
110
2
70
0.03
2
86
0.31
2
106
–0.44
150
1
207
0.16
1
255
0.00
2
77
0.16
300
1
103
0.16
1
127
0.00
1
155
0.16
600
0
207
0.16
0
255
0.00
1
77
0.16
1200
0
103
0.16
0
127
0.00
0
155
0.16
2400
0
51
0.16
0
63
0.00
0
77
0.16
4800
0
25
0.16
0
31
0.00
0
38
0.16
9600
0
12
0.16
0
15
0.00
0
19
–2.34
14400
0
8
–3.55
0
10
–3.03
0
12
0.16
19200
0
6
–6.99
0
7
0.00
0
9
–2.34
28800
0
3
8.51
0
4
6.67
0
6
–6.99
31250
0
3
0.00
0
4
–1.70
0
5
0.00
38400
0
2
8.51
0
3
0.00
0
4
–2.34



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