SH7041A datasheet(568/923 Pages) RENESAS

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to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to

clear the error flag.

3.After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the

SCR, the SCI requests a receive-data-full interrupt (RxI). If the ORER bit is set to 1 and the

receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a

receive-error interrupt (ERI).

Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure

14.23 shows a sample flowchart for transmitting and receiving serial data simultaneously. The

procedure is as follows (the steps correspond to the numbers in the flowchart):

1.SCI initialization: Set the TxD and RxD pins using the PFC.

2.SCI status check and transmit data write: Read the serial status register (SSR), check that the

TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to

0. The TxI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1.

3.Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the

error. After executing the necessary error processing, clear ORER to 0. Transmitting/receiving

cannot resume if ORER remains set to 1.

4.SCI status check and receive data read: Read the serial status register (SSR), check that RDRF

is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.

The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.

5.Continue transmitting and receiving serial data: Read the RDRF bit and RDR, and clear RDRF

to 0 before the frame MSB (bit 7) of the current frame is received. Also read the TDRE bit to

check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0

before the MSB (bit 7) of the current frame is transmitted. When the DMAC or the DTC is

started by a transmit-data-empty interrupt request (TxI) to write data in TDR, the TDRE bit is

checked and cleared automatically. When the DMAC or the DTC is started by a receive-data-

full interrupt (RxI) to read RDR, the RDRF bit is cleared automatically.

Note:

In switching from transmitting or receiving to simultaneous transmitting and receiving,

simultaneously clear both TE and RE to 0, then simultaneously set both TE and RE to 1.

SH7041A Datasheet(PDF) 568 Page - Renesas Technology Corp