SH7041A datasheet(572/923 Pages) RENESAS

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14.5.3

Break Detection and Processing

Break signals can be detected by reading the RxD pin directly when a framing error (FER) is

detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the

parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so

if the FER bit is cleared to 0, it will be set to 1 again.

14.5.4

Sending a Break Signal

The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O port

data register (DR) and pin function controller (PFC) control register (CR). These conditions allow

break signals to be sent. The DR value is substituted for the marking status until the PFC is set.

Consequently, the output port is set to initially output a 1. To send a break in serial transmission,

first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When TE is

cleared to 0, the transmission section is initialized regardless of the present transmission status.

14.5.5

Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only)

When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting

even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit.

Note that clearing RE to 0 does not clear the receive error flags.

14.5.6

Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode

In the asynchronous mode, the SCI operates on a base clock of 16 times the bit rate frequency. In

receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on

the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure

14.24).

SH7041A Datasheet(PDF) 572 Page - Renesas Technology Corp