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SH7041A Datasheet(PDF) 573 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 573 Page - Renesas Technology Corp |
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573 / 923 page  535 07 8 15 0 7 8 15 0 5 Internal base clock Receive data (RxD) Synchronization sampling timing Data sampling timing 8 clocks 16 clocks Start bit –7.5 clocks +7.5 clocks D0 D1 Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in the asynchronous mode can therefore be expressed as: M = 0.5 – 1 2N – L – 0.5 F – D – 0.5 N 1 + F 100% () ( ) × M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0–1.0) L : Frame length (L = 9–12) F : Absolute deviation of clock frequency From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%: D = 0.5, F = 0 M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20–30%. |
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