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SH7041A Datasheet(PDF) 627 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 627 Page - Renesas Technology Corp |
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627 / 923 page ![]() 589 17.1.3 Register Configuration Table 17.1 summarizes the CMT register configuration. Table 17.1 Register Configuration Channel Name Abbreviation R/W Initial Value Address Access Size (Bits) Shared Compare match timer start register CMSTR R/W H'0000 H'FFFF83D0 8, 16, 32 0 Compare match timer control/status register 0 CMCSR0 R/(W)* H'0000 H'FFFF83D2 8, 16, 32 Compare match timer counter 0 CMCNT0 R/W H'0000 H'FFFF83D4 8, 16, 32 Compare match timer constant register 0 CMCOR0 R/W H'FFFF H'FFFF83D6 8, 16, 32 1 Compare match timer control/status register 1 CMCSR1 R/(W)* H'0000 H'FFFF83D8 8, 16, 32 Compare match timer counter 1 CMCNT1 R/W H'0000 H'FFFF83DA 8, 16, 32 Compare match timer constant register 1 CMCOR1 R/W H'FFFF H'FFFF83DC 8, 16, 32 Note: * The only value that can be written to the CMCSR0 and CMCSR1 CMF bits is a 0 to clear the flags. |
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