SH7041A datasheet(672/923 Pages) RENESAS

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18.3.12

Port D Control Register L (PDCRL)

PDCRL is a 16-bit read/write register that selects the multiplexed pin functions for the least

significant sixteen port D pins. There are instances when these register settings will be ignored,

depending on the operation mode.

On-Chip ROM-Disabled Extended Mode:

• 144-pin version:

 Mode 0 (16-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.

 Mode 1 (32-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.

• 112-pin and 120-pin versions:

 Mode 0 (8-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.

 Mode 1 (16-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.

On-Chip ROM-Enabled Extended Mode: The port D pins are shared as data I/O pins and

general I/O pins; PDCRL settings are enabled.

Single Chip Mode: The port D pins are general I/O pins; PDCRL settings are disabled.

PDCRL is initialized to H'0000 by external power-on reset but is not initialized for manual resets,

reset by WDT, standby mode, or sleep mode, so the previous data is maintained.

Port D Control Register L (PDCRL)

Bit:

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

Initial value:

R/W:

R/W

Bit:

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Initial value:

R/W:

R/W

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