SH7041A datasheet(727/923 Pages) RENESAS

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22.3

Pin Configuration

The flash memory is controlled by the pins shown in table 22.2.

Table 22.2

Pin Configuration

Pin Name

Abbreviation

I/O

Function

Power-on reset

RES

Input

Power-on reset

Flash write protect

FWP

Input

Flash program/erase protection by hardware

Mode 3

MD3

Input

Set operation mode of LSI

Mode 2

MD2

Input

Set operation mode of LSI

Mode 1

MD1

Input

Set operation mode of LSI

Mode 0

MD0

Input

Set operation mode of LSI

Transmit data

TxD1

Output

Serial send data output

Receive data

RxD1

Input

Serial receive data input

22.4

Registers that control the flash memory when the on-chip flash memory is valid are shown in table

22.3.

Table 22.3

Name

Abbre-

viation

R/W

Initial Value

Address

Access Size

Flash memory control register 1

FLMCR1 R/W*

H'00*

H'FFFF8580 8

Flash memory control register 2

FLMCR2 R/W*

H'00*

H'FFFF8581 8

Erase block register 1

EBR1

R/W*

H'00*

H'FFFF8582 8

Erase block register 2

EBR2

R/W*

H'00*

H'FFFF8583 8

RAM emulation register

RAMER

R/W

H'0000

H'FFFF8628 8, 16, 32

Notes: 1. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers, and RAMER is a 16-bit

2. Only byte accesses are valid for FLMCR1, FLMCR2, EBR1, and EBR2, the access

requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and

6 cycles for a longword access.

3. When a longword write is performed on RAMER, 0 must always be written to the lower

word (address H'FFFF8630). Operation is not guaranteed if any other value is written.

*1 In modes in which the on-chip flash memory is disabled, a read will return H'00, and

writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1.

*2 When a low level is input to the FWP pin, the initial value is H'80.

*3 When a high level is input to the FWP pin, or if a low level is input and the SWE bit in

FLMCR1 is not set, these registers are initialized to H'00.

SH7041A Datasheet(PDF) 727 Page - Renesas Technology Corp

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