SH7041A datasheet(188/923 Pages) RENESAS

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The total transfer count is specified between 1 and 256. When the specified number of transfers

ends, the address register of the designated repeat area is returned to its initial state and the transfer

is repeated. Other address registers are consecutively incremented, decremented, or remain fixed.

While DISEL = 0, no interrupt request is made to the CPU, even if the transfer with DTCRAL = 1

ends.

Pulses for driving the stepping motor can be output. Table 8.4 shows the register functions for

repeat mode.

Table 8.4

Repeat Mode Register Functions

Values Written Back upon a

Transfer Information Write

Function

When DTCRA is

other than 1

When DTCRA is 1

DTMR

Operation mode

control

DTMR

DTCRAH

Transfer count

maintenance

DTCRAH

DTCRAL

Transfer count

DTCRAL – 1

DTCRAH

DTIAR

Initial address

(Not written back)

DTSAR

Transfer source

address

Increment/decrement/

fixed

(DTS = 0) Increment/

decrement/ fixed

(DTS = 1) DTIAR

DTDAR

Transfer destination

address

Increment/decrement/

fixed

(DTS = 0) DTIAR

(DTS = 1) Increment/

decrement/ fixed

8.3.7

Block Transfer Mode

Performs the transfer of one block for each one activation. Either the transfer source or transfer

destination is designated as the block area.

The block length is specified between 1 and 65536. When a 1-block transfers ends, the address

consecutively incremented, decremented, or remain fixed. The block transfer count is 1 to 65536.

An interrupt request is generated to the CPU when the transfer with DTCRA = 1 ends.

A/D converter group mode transfers and phase compensation PWM data transfers are possible.

Table 8.5 shows the register functions for block transfer mode.

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