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SH7041A Datasheet(PDF) 193 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 193 Page - Renesas Technology Corp |
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193 / 923 page  155 Section 9 Cache Memory (CAC) 9.1 Overview The LSI has an on-chip cache memory (CAC) with 1 kbyte of cache data and a 256-entry cache tag. The cache data and cache tag space can be used as on-chip RAM space when the cache is not being used. 9.1.1 Features The CAC has the following features. The cache tag and cache data configuration is shown in figure 9.1. • 1-kbyte capacity • External memory (CS space and DRAM space) instruction code and PC relative data caching • 256 entry cache tag (tag address 15 bits) • 4-byte line length • Direct map replacement algorithm • Valid flag (1 bit) included for purges Cache tag 256 entries Data (32 bits) Tag address (15 bits) Cache data Data bus Hit signal CPU address Tag address Entry address Offset Valid bit (1 bit) CMP 15 8 2 Figure 9.1 Cache Tag and Cache Data Configuration |
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