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SH7041A Datasheet(PDF) 267 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 267 Page - Renesas Technology Corp |
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267 / 923 page  229 Figure 11.2 is a flowchart of this procedure. Normal end Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Bus mode, transfer request mode, DREQ detection selection system Initial settings (SAR, DAR, TCR, CHCR, DMAOR) Transfer (1 transfer unit); DMATCR – 1 → DMATCR, SAR, and DAR updated DEI interrupt request (when IE = 1) No Yes No Yes No Yes Yes No Yes No *3 *2 Start Transfer aborted Notes: *1 *2 *3 In auto-request mode, transfer begins when NMIF, AE, and TE are all 0, and the DE and DME bits are set to 1. DREQ = level detection in burst mode (external request), or cycle-steal mode. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode. DMATCR = 0? Transfer request occurs?*1 DE, DME = 1 and NMIF, AE, TE = 0? Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Transfer ends Figure 11.2 DMAC Transfer Flowchart |
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