SH7041A datasheet(263/923 Pages) RENESAS

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• Bit 5—Transfer Mode (TM): Specifies the bus mode for data transfer.

Bit 5: TM

Description

Cycle steal mode (initial value)

Burst mode

• Bits 4 and 3—Transfer Size 1, 0 (TS1, TS0): Specifies size of data for transfer.

Bit 4: TS1

Bit 3: TS0

Description

Specifies byte size (8 bits) (initial value)

Specifies word size (16 bits)

Specifies longword size (32 bits)

Prohibited

• Bit 2—Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the

number of data transfers specified in the DMATCR (when TE = 1).

Bit 2: IE

Description

Interrupt request not generated after DMATCR-specified transfer count

(initial value)

Interrupt request enabled on completion of DMATCR specified number

of transfers

• Bit 1—Transfer End Flag (TE): This bit is set to 1 after the number of data transfers specified

by the DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.

If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or

clearing of the DE bit or DME bit of the DMAOR) the TE is not set to 1. With this bit set to 1,

data transfer is disabled even if the DE bit is set to 1.

Bit 1: TE

Description

DMATCR-specified transfer count not ended (initial value)

Clear condition: 0 write after TE = 1 read, Power-on reset, standby

mode

DMATCR specified number of transfers completed

SH7041A Datasheet(PDF) 263 Page - Renesas Technology Corp