SH7041A datasheet(310/923 Pages) RENESAS

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11.5

Cautions on Use

1. Other than the DMA operation register (DMAOR) accessing in word (16-bit) units, access all

registers in word (16-bit) or longword (32-bit) units.

2. When rewriting the RS0–RS3 bits of CHCR0–CHCR3, first clear the DE bit to 0 (set the DE

bit to 0 before doing rewrites with a CHCR byte address).

3. When an NMI interrupt is input, the NMIF bit of the DMAOR is set even when the DMAC is

not operating.

4. Set the DME bit of the DMAOR to 0 and make certain that any DMAC received transfer

request processing has been completed before entering standby mode.

5. Do not access the DMAC, DTC, BSC, or UBC on-chip peripheral modules from the DMAC.

6. When activating the DMAC, do the CHCR or DMAOR setting as the final step. There are

instances where abnormal operation will result if any other registers are established last.

7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write a 0 to

the DMATCR, even when executing the maximum number of transfers on the same channel.

There are instances where abnormal operation will result if this is not done.

8. Designate burst mode as the transfer mode when using the address reload function. There are

instances where abnormal operation will result in cycle steal mode.

9. Designate a multiple of four for the DMATCR value when using the address reload function.

There are instances where abnormal operation will result if anything else is designated.

10. When detecting external requests by falling edge, maintain the external request pin at high

level when performing the DMAC establishment.

11. When operating in single address mode, establish an external address as the address. There are

instances where abnormal operation will result if an internal address is established.

12. Do not access DMAC register empty addresses (H'FFFF86B2–H'FFFF86BF). Operation

cannot be guaranteed when empty addresses are accessed.

SH7041A Datasheet(PDF) 310 Page - Renesas Technology Corp