SH7041A datasheet(306/923 Pages) RENESAS

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Table 11.10 DMAC Internal Status

Item

Address Reload On

Address Reload Off

SAR

H'FFFF83F0

H'FFFF83F4

DAR

H'FFFFF004

DMATCR

H'0000007C

Bus rights

Released

Maintained

DMAC operation

Halted

Processing continues

Interrupts

Not issued

Transfer request source flag clear

Executed

Not executed

Notes: 1. Interrupts are executed until the DMATCR value becomes 0, and if the IE bit of the

CHCR is set to 1, are issued regardless of whether the address reload is on or off.

2. If transfer request source flag clears are executed until the DMATCR value becomes 0,

they are executed regardless of whether the address reload is on or off.

3. Designate burst mode when using the address reload function. There are cases where

abnormal operation will result if it is executed in cycle steal mode.

4. Designate a multiple of four for the TCR value when using the address reload function.

There are cases where abnormal operation will result if anything else is designated.

To execute transfers after the fifth one when the address reload is on, make the transfer request

source issue another transfer request signal.

11.4.4

Example of DMA Transfer between A/D Converter and Internal Memory (Address

Reload On) (A Mask)

In this example the on-chip A/D converter (A/D1) is the transfer source and the internal memory is

the transfer destination, and the address reload on.

Table 11.11 indicates the transfer conditions and the setting values of each of the registers.

SH7041A Datasheet(PDF) 306 Page - Renesas Technology Corp