SH7041A datasheet(305/923 Pages) RENESAS

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Table 11.9

Transfer Conditions and Register Set Values for Transfer between A/D

Converter and On-Chip Memory

Transfer Conditions

Value

Transfer source: on-chip A/D converter ch0

SAR2

H'FFFF83F0

Transfer destination: on-chip memory

DAR2

H'FFFFF000

Transfer count: 128 times (reload count 32 times)

DMATCR2

H'00000080

Transfer source address: incremented

CHCR2

H'00085B25

Transfer destination address: incremented

Transfer request source: A/D converter

Bus mode: burst

Transfer unit: byte

Interrupt request generation at end of transfer

Channel priority ranking: 0

> 2 > 3 > 1

DMAOR

H'0101

When address reload is on, the SAR value returns to its initially established value every four

transfers. In the above example, when a transfer request is input from the A/D converter, the byte

size data is first read in from the H'FFFF83F0 register of AD0 and that data is written to the on-

chip memory address H'FFFFF001. Because a byte size transfer was performed, the SAR and

DAR values at this point are H'FFFF83F1 and H'FFFFF001, respectively. Also, because this is a

burst transfer, the bus rights remain secured, so continuous data transfer is possible.

When four transfers are completed, if the address reload is off, execution continues with the fifth

and sixth transfers and the SAR value continues to increment from H'FFFF83F3 to H'FFFF83F4 to

H'FFFF83F5 and so on. However, when the address reload is on, the DMAC transfer is halted

upon completion of the fourth one and the bus right request signal to the CPU is cleared. At this

time, the value stored in SAR is not H'FFFF83F3–H'FFFF83F4, but H'FFFF83F3–H'FFFF83F0, a

return to the initially established address. The DAR value always continues to be decremented

regardless of whether the address reload is on or off.

The DMAC internal status, due to the above operation after completion of the fourth transfer, is

indicated in table 11.10 for both address reload on and off.

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