SH7041A datasheet(303/923 Pages) RENESAS

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When the processing of a one unit transfer is complete. In a dual address mode direct address

transfer, even if an address error occurs or the NMI flag is set during read processing, the

transfer will not be halted until after completion of the following write processing. In such a

case, SAR, DAR, and TCR values are updated. In the same manner, the transfer is not halted in

dual address mode indirect address transfers until after the final write processing has ended.

• When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR aborts the

transfers on all channels. The TE bit is not set.

11.3.13

DMAC Access from CPU

The space addressed by the DMAC is 3-cycle space. Therefore, when the CPU becomes the bus

master and accesses the DMAC, a minimum of three basic clock (CLK) cycles are required for

one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the

DMAC is completed in one bus cycle, a longword-size access is automatically divided into two

word accesses, requiring two bus cycles (six basic clock cycles). These two bus cycles are

executed consecutively; a different bus cycle is never inserted between the two word accesses.

This applies to both write accesses and read accesses.

11.4

Examples of Use

11.4.1

Example of DMA Transfer between On-Chip SCI and External Memory

In this example, on-chip serial communication interface channel 0 (SCI0) received data is

transferred to external memory using the DMAC channel 3.

Table 11.7 indicates the transfer conditions and the setting values of each of the registers.

Table 11.7

Transfer Conditions and Register Set Values for Transfer between On-Chip

SCI and External Memory

Transfer Conditions

Value

Transfer source: RDR0 of on-chip SCI0

SAR3

H'FFFF81A5

Transfer destination: external memory

DAR3

H'00400000

Transfer count: 64 times

DMATCR3

H'00000040

Transfer source address: fixed

CHCR3

H'00004D05

Transfer destination address: incremented

Transfer request source: SCI0 (RDR0)

Bus mode: cycle steal

Transfer unit: byte

Interrupt request generation at end of transfer

Channel priority ranking: 0

> 1 > 2 > 3

DMAOR

H'0001

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