MPC8548EEC datasheet(23/151 Pages) NXP

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

DDR and DDR2 SDRAM

6.2.2

DDR SDRAM Output AC Timing Specifications

Table 19. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions.

Parameter

Symbol1

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

tMCK

3.75

ADDR/CMD output setup with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHAS

1.48

1.95

2.40

—

ADDR/CMD output hold with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHAX

1.48

1.95

2.40

—

MCS[n] output setup with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHCS

1.48

1.95

2.40

—

MCS[n] output hold with respect to MCK

533 MHz

400 MHz

333 MHz

tDDKHCX

1.48

1.95

2.40

—

MCK to MDQS Skew

tDDKHMH

–0.6

0.6

MDQ/MECC/MDM output setup with respect

to MDQS

533 MHz

400 MHz

333 MHz

tDDKHDS,

tDDKLDS

538

700

900

—

MDQ/MECC/MDM output hold with respect to

MDQS

533 MHz

400 MHz

333 MHz

tDDKHDX,

tDDKLDX

538

700

900

—

MDQS preamble start

tDDKHMP

–0.5

× tMCK – 0.6

–0.5

× tMCK + 0.6

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